1. Field of the Invention
The present invention relates to a clock generator, and more particularly, to a clock generator for generating multiple clock signals having different phases.
2. Description of the Related Art
In order to test the reliability of a semiconductor device, a bit error rate (BER) is measured. For example, a dynamic random access memory (DRAM) restores a signal received from an external device (a measuring device of a memory controller) and transmits the restored signal back to the measuring device, or operations of an interface circuit between a transmitter and a receiver are verified by decision in a DRAM chip. As a method of testing the bit error rate, the DRAM receives and outputs data applied from the external device to test whether the DRAM can detect and output the received data. The external device used to measure the bit error rate may be automated test equipment (ATE).
FIG. 1A is a block diagram illustrating a conventional device for measuring bit error rate.
Referring to FIG. 1A, data signal S_DATA output from ATE device 110 is input to DRAM 101. The ATE device 110 also outputs a clock signal S_CLK needed to observe the data signal S_DATA and a waveform of the data signal. Phase and magnitude of the clock signal S_CLK are swept by very small values, and clock signals S_CLKs having different phases and magnitudes are continuously output.
The DRAM 101 receives, detects and outputs the data S_DATA. A signal detected by and output from the DRAM 101 is observed by an error checker (e.g., denoted by reference numeral 115 in FIG. 1B) in the DRAM 101 or the ATE device 110. The error checker 115 in the DRAM 101 or the ATE device 110 determines whether the DRAM 101 properly receives and outputs a signal that the DRAM 101 initially transmits.
FIG. 1B is a block diagram illustrating the measuring device of FIG. 1A, in detail.
Referring to FIG. 1B, the data S_DATA output from the ATE device 110 is transmitted to the DRAM 101. The ATE device 110 internally generates clock signal CLK and outputs the clock signal S_CLK, which is generated by delaying the clock signal CLK by a predetermined delay amount in delay line 113.
The DRAM 101 may include error checker and counter 115. Alternatively, the error checker 115 may be included in an external tester. The error checker and counter 115 may be any type of element for detecting data transmission errors. The bit error rate test is performed when the ATE device 110 receives the S_DATA, including a predetermined offset voltage, and the clock signal S_CLK which is precisely phase-controlled, and the error checker and counter 115 observes a waveform of a signal output according to the data signal S_DATA and the clock signal S_CLK.
FIG. 2A is a view illustrating an initial measuring process of the device for measuring the bit error rate in FIG. 1B.
A curve 201 is a waveform of a data signal measured by a front end of a receiver 122 of the DRAM 101. S_DATA transmitted from the ATE device 110 or the memory controller to the DRAM 101 has the same waveform as that of the curve 201, referred to as an “eye diagram.” In the illustrated eye diagram, the x-axis represents time, and the y-axis represents voltage values. One-bit data is transmitted during a time interval from time point (a) to time point (b). In addition, a signal value of a logic low voltage level is determined as value (d), and a signal value of a logic high voltage level is determined as value (c).
Referring to FIG. 2A, a test of detecting an error of 1-bit data signal S_DATA may be started at the time point (a). Image 210 represents a result of the test.
The error checker and counter 115 measures the waveform of the data signal detected by and output from the DRAM 101 over the entire interval. Therefore, the test is started at time point (a) and performed by changing a time point (measuring time) and a voltage value by very small values.
For example, it may be assumed that a cycle of a 1-bit data signal is 450 ps (pico seconds). By shifting the applied clock by 5 ps, for example, the entire waveform interval of the data signal S_DATA is observed. The period of 450 ps is observed by intervals of 5 ps, so that an observation time point is shifted 90 times. In other words, by continuously changing the clock phase, clock signal S_CLK is output. In addition, in response to the clock signal S_CLK applied by the ATE device 110, the error checker and counter 115 observes the waveform in the time-axis direction of the data signal S_DATA.
Assuming that amplitude of the data signal S_DATA is 100 mV, the ATE device 110 outputs the data signal S_DATA, including an offset voltage signal, by shifting the voltage by 2 mV.
FIG. 2B is a view illustrating an intermediate measuring process of the device in FIG. 1B.
Referring to FIG. 2B, the ATE device 110 delays applying the clock signal by an interval obtained by subtracting time point (a) from time point (e). The ATE device 110 shifts the offset voltage value to point (f) to observe the waveform of the data signal.
FIG. 2C is a view illustrating the last measuring process of the device in FIG. 1B.
Referring to FIG. 2C, when measuring is performed on the last portion of the one-cycle data signal waveform, a waveform as illustrated in image 230 is measured. Specifically, when data in the shape of the eye diagram is transmitted, the waveform having similar or the same shape is represented in the image 230, so that it is determined that a corresponding bit of a corresponding semiconductor device is normal.
By magnifying the image 230, it can be seen that a fine eye diagram shown by curve 270 is output, indicating a normal test. The ATE device 110 delays the clock signal by a very small value at time points 271, 272 and 273, to be applied. In addition, by changing the offset voltage from values 281, 282 and 283 by very small amounts to be applied to the data signal S_DATA, the test is performed.
As described above, in order to measure the bit error rate of the semiconductor device, the clock must be applied while delicately shifting the time interval. In addition, the applied time interval must be a very small value, such as 5 ps, exemplified above. When a very small value is applied as the time interval, the more accurate eye diagram can be obtained, and the more accurate test can be performed.
However, for the time sweep of the clock signal, the ATE device having a very small interval has high costs, and it is difficult to transmit multi-phase clock signals. In addition, for mount measurements, a test between the memory controller and the DRAM is required.